1. Field of the Invention
This invention is provided for verification of algorithms in order to facilitate architecture designs at high-level stages of design. Specifically, this invention relates to bus performance evaluation methods for algorithm descriptions in which evaluation is performed on performances of buses interconnecting between the hardware and software by use of sources described by general purpose high-level languages such as the C language and C++ language.
2. Description of the Related Art
Due to the recent developments of the semiconductor technologies, there are tendencies for the physical hardware system to be frequently actualized by a single LSI chip rather than by plural LSI chips arranged on boards. For this reason, signals of the LSI chips that are conventionally interconnected with external terminals are translated to internal signals and are incorporated within the LSI chips in these days. To verify the conventional systems using the boards, it is necessary to produce LSI devices specifically for use in evaluation that is performed as if all internal signals are interconnected with external terminals. However, it is troublesome for manufacturers to perform verification on the systems by using the specifically designed LSI devices. Actually, the recent developments raise a difficulty in which verification is difficult to perform using the foregoing boards.
FIG. 11 shows a flow of steps showing the conventional procedures for the design and development of LSI (hereinafter, simply referred to as LSI design and development) in manufacture of logic circuits, systems and devices. Prior to the actual manufacturing, simulation programs (or algorithms) are normally structured without consideration of distinctions between the hardware and software (see step B1). In step B2, verification is made as to whether the algorithms are correctly made or not. Next, isolation of the hardware and software is performed on the structured simulation program, which are divided into hardware elements and software elements of the simulation program respectively. The isolation of the hardware and software is made by experimentation.
In the hardware design (or H/W design), elements having equivalent functions of the algorithms are generally described by equivalent HDL source code(which stands for ‘Hardware Description Language’), then, composition of circuitry is carried out (see step B3). In step B4, verification is made as to whether the sources operate correctly or not. In the software design (or S/W design), elements having equivalent functions of the algorithms are generally described by equivalent source code of a programming language having a CPU dependency (see step B5). In step B6, verification is made as to whether the sources operate correctly or not. Lastly, cooperative verification is performed on combinations of the hardware and software (see step B7).
Prior to the actual manufacturing of LSI, the procedures for the LSI design and development should meet some essential conditions regarding requirements of the system simulation and bus performance evaluation as well as the architecture design in which isolation of the hardware and software is performed by simulation. Conventionally, the system simulation is performed by the cooperative verification on the unification of the hardware and software.
Due to rapid increases in scales of integrated circuits being manufactured in these days, it becomes necessary to provide considerably large numbers of lines of codes to describe the circuits to be created. This causes considerable reduction in simulation speed of the cooperative verification on descriptions using the HDL or other programming languages each having a CPU dependency. In practice, it becomes very difficult to perform the architecture design using the cooperative verification.
In the architecture design using the cooperative verification, there may occur necessities of modifications on buses interconnecting said elements to be implemented in the hardware and/or in software due to results of evaluation of performances of the buses. In that case, it is necessary to modify the HDL or other programming languages each having a CPU dependency (see steps B8, B9 in FIG. 11).
Due to increasing numbers of lines of codes to describe the circuits to be created, circuit descriptions must become more and more complicated, which in turn cause complexity in modifications of the circuit descriptions. That is, it takes much time and cost to perform operations regarding feedback loops being derived from results of the cooperative verification. Recently, there are tendencies in which periods for developments of LSI are considerably reduced while the circuit scales are increased more and more. To cope with such tendencies, the procedures of the LSI design and development should meet some essential conditions in which evaluation of performances of the buses interconnecting elements to be implemented in hardware and/or in software and the architecture design are performed at high-level stages of design respectively.